1. Field of the Invention
The present invention relates to a carrier structure for a semiconductor chip and a method for manufacturing the same, and especially, to a method for manufacturing a carrier structure having a cavity in which a semiconductor chip is disposed.
2. Description of Related Art
Customer demands of the electronics industry continue to evolve rapidly and the main trends are high integration and miniaturization. In order to satisfy those requirements, especially in the packaging of semiconductor devices, development of packaging substrates sufficing active and passive components and conductive wires has progressed from single layer to multiple layers. This means that a greater usable area is available due to interlayer connection technology.
In the conventional semiconductor device, semiconductor chips are mounted on the front side surface of a substrate by its inactive surface, and then are processed by wire bonding, or semiconductor chips are directly conducted by its active surface with the front side surface of a substrate by flip-chip technology. After that, solder balls are implanted on the back side surface of the substrate to provide electrical connections for a printed circuit board. Although an objective of high quantity pin counts is achieved, it is limited that electric characteristics are unable to be improved in higher-frequency and higher-speed operation due to long pathways of conductive wires.
In many studies, semiconductor chips directly electrically connecting to external electronic devices are embedded into a packaging substrate to shorten conductive pathways, to decrease signal loss and distortion, and to increase abilities of high-speed operation.
In a carrier structure having a chip embedded therein, as shown in FIG. 1, metal layers are added on electrode pads of an active surface of the chip for preventing destruction by laser ablation of the chip in a carrier. The carrier structure having a chip embedded therein includes: a carrier board 11 having a through cavity 110 formed therein; a chip 12 placed in the cavity 110, wherein the active surface of the chip 12 has a plurality of electrode pads 13 thereon; a protective layer 14, having a plurality of openings 140 exposing the electrode pads 13, formed on the active surface of the chip 12; a plurality of metal layers 15 formed on surfaces of the electrode pads 13; and a built-up structure 16 formed on the active surface of the chip 12 and on one surface of the carrier board 11 on the same side with the active surface of the chip 12. The built-up structure 16 has a plurality of conductive vias 161 to electrically connect the electrode pads 13 of the chip 12.
Currently, in a carrier structure embedded with chips, the cavity of the carrier board is used for disposing the chip. However, a gap exists between the chip and the carrier board. Prior to fixing the chip, tiny shifts occur inevitably. Therefore, alignment errors caused by the shifts of the chip are already greater than those resulted from formation of via holes by laser ablation. In order to benefit circuit layers to electrically connect the electrode pads, those pads of the chip have to be formed in a size about 200˜250 μm. Accordingly, alignment by laser ablation will be more available during the formation of built-up structures, and failure of alignment will not occur, thus avoiding destruction of the chip. Nevertheless, the greater electrode pads of the semiconductor can not satisfy the demand of circuit miniaturization nowadays. On the other hand, due to aforementioned alignment errors, panels used during manufacturing circuit layer have to be exposed many times in part to control alignment errors being smaller, hence manufacturing processes are difficult to be simplified. Conclusively, prior arts do not satisfy the requirements of circuit miniaturization, and are not capable of following the trends of compact semiconductor packages.
Furthermore, an adhesive material is required to fill in the gap between the chip and the cavity of the carrier board so that the problem of excess adhesive material spilling out of the gap prior to solidification can occur. In order to avoid the problem illustrated above, complexity of the manufacturing processes will be unavoidably increased. Finally, problems of stress between different materials still occur in prior arts to cause warpage, delamination, or popcorn of the carrier board. Therefore, those problems have become imperative issues to be solved by the industry.